Posts

Behavioral Modeling I

Data flow modeling

Gate level Modelling

Gate delays

Basics : Data Types III

Basics : Data types II

Basics : Data Types I

Synchronous Reset and Asynchronous Reset

CHISEL : Vec

CHISEL : Bundle

n bit binary adder or ripple carry adder

CHISEL: Counter in Chisel

scan cell, scan chain

scan chain REORDERING , why it is required

Untestable faults in DFT

Fault Class Hierarchies in DFT

Implement the inverter using nand/NOR gate

Different ways of Digital design representation

Simplistic view of ASIC DESIGN flow

chisel:Registers