In digital design, register are the basic elements which are used widely. Chisel provides a register , which is collection of D Flip Flops. The register is connected to a clock and the output of the register updates on every rising edge. When an initialization value is provided at the declaration of thr register, it uses a synchronous reset connected to reset signal. A register can be any chisel type that can be represented as a collection of bits.
Below line defines an 8 bit register, initialized with 0 at reset:
val reg = RegInit(0.U(8.W))
An input is connected to the register with the := update operator and the output of the register can be used just with the name in an expression
reg := d
val q = reg
A register can also be connected to its input at the definition:
val nextReg = RegNext(d)
A register can also be initialized during the definition:
val bothReg = RegNext(d, 0.U)
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