Simplistic view of ASIC DESIGN flow

Steps in design flow

  • Behavioral Design
    • Specifies the functionality of the chip
  • Data path Design
    • Generates the netlist for the register transfer level components
  • Logic Design
    • Generate the netlist of Gates/Flip-Flops or Standard cells
  • Physical Design
    • Generate the final layout
  • Manufacturing the chip in Fabrication unit

Some more Intermediate steps are required during the Design flow.

  • Simulation for Verification
    • It should be carried out at various levels, which includes: Logic level, Switch level, Circuit level
  • Formal Verification
    • Logical equivalence check will be carried at various levels, to check core design was not disturbed.
    • LEC/Formal Verification on the design was done between
      -RTL and Synthesised Netlist
      -Synthesized Netlist and DFT inserted Netlist
      -MBIST Inserted Netlsit and Synthesized Netlist, etc
  • Testability analysis and Pattern Generation
    • Required to test the manufactured Devices