Posts

how to design the better transistor which has high on current and low off current

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Setup time and Hold Time

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Design For Testability

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Temperature effects on Mobility

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Drive Strength of devices

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False Paths:set_false_path

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Clock Gating

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Technology/Process node

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Why mosfet are replaced by FD-SOI ,Finfet below 28nm technology?

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Difference between LEF and DEF files

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In scan chain why negative edge flops are followed by positive edge flip flops

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Unix Basic Commands III

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Unix Basic Commands II

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Unix Basic Commands I

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Can hold violation be removed after chip was fabricated

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SDC (Synopsys design Constraints)

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Welcome to VLSI SPACE

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