Blockages:
Let’s assume that for some reason you don’t want to place any logic (can be a specific set of cells as well) or you don't intend to allow certain metal layers in a specific area or you are reserving a space for later stage additions (could be a room for top design related ) :
in all these cases you can use ‘blockages’ to reserve/restrict/block a specific area either from preventing std cell placement or avoiding specific layer metal shapes.
1. placement blockages
2. routing blockages.
Halos:
In the design of a System-on-Chip (SoC) comprising multiple sub-IPs/blocks, the physical implementation of both the top-level SoC and its sub-blocks is typically managed by distinct teams. To ensure that the physical layout adheres to design rules and is fabrication-ready upon integration, a coordinated approach is essential. This involves guidance from the methodology, fabrication, and process teams to establish standardized layout patterns for all designs, particularly at their boundaries. This best practice enables the top-level designer to anticipate interface patterns and implement integration strategies effectively. To facilitate this, the implementation of HALO cells, incorporating recommended patterns for various edge types, is proposed. Both sub-blocks and the top-level design must utilize these HALO cells appropriately on all sides.
