TIE CELLS

To prevent direct gate connections to the power or ground network, tie-high and tie-low cells are employed. Within this design, certain cell inputs may necessitate a logic 0 or logic 1 value. Unused cell inputs are also connected to ground or power nets, as leaving them unconnected is not permissible. Rather than directly connecting these inputs to the VDD/VSS rails/rings, they are connected to specialized cells within the library, known as TIE cells

The tie-high, tie-low circuit, featuring tie-high and tie-low outputs, incorporates a regenerative device designed for connection to both outputs, along with at least one PMOS device and one NMOS device, intended for connection to a high voltage and a low voltage, respectively.

In integrated circuit (IC) applications, it is not always necessary to utilize all inputs. Unused inputs should be consistently maintained in a stable logic state, rather than left floating, as unpredictable or intermediate logic states can lead to unpredictable and inconsistent logical outcomes. This is a critical concern that IC designers actively address.

To ensure stability, small circuits are incorporated into ICs. These circuits typically provide at least two outputs: one consistently high and another consistently low. These outputs are then used to connect IC inputs to either a high or low state, thereby locking unused inputs into a stable logic state.

However, conventional circuit designs present several challenges. Many designs utilize at least four transistors, which consume valuable chip area and may necessitate additional, costly manufacturing steps. Furthermore, some designs, while using only three transistors, often exhibit limited tolerance to electrostatic discharge (ESD).

Consequently, there is a need in the field of integrated circuit design for improved, smaller circuits with enhanced ESD tolerance, capable of effectively tying unused IC inputs to either a high or low state.

Regarding the rationale for employing such circuits, gate oxide is inherently thin and sensitive to voltage surges. Certain manufacturing processes may restrict the direct connection of gates to power rails due to the potential for gate oxide damage from voltage surges, such as ESD events. Therefore, tie cells, which utilize diode-connected n-type or p-type devices, are often employed. This approach prevents direct gate connections to either power or ground.

This is the foundry's rationale for ESD protection against surges. Examining the schematic of the tie cells in a standard cell library may reveal an inverter configuration with its input connected to either VDD (for tie-low) or VSS (for tie-high). While this configuration still connects the tie cell's gate to the power rails, it offers benefits such as reduced leakage current. Additionally, it simplifies the process of rewiring during Engineering Change Orders (ECOs), particularly when swapping a 1'b1 for a 1'b0.