Different ways to Fix Setup or Hold VIOLATIONS in a design during PnR

How do I fix setup or hold violation during placement?

Setup and hold violations represent crucial timing constraints that can arise during the placement phase of digital circuit design, especially within ASIC and FPGA implementations. The following outlines a comprehensive methodology for identifying and rectifying these violations.

Understanding Setup and Hold Violations

Setup Violation: A setup time violation occurs when the data input to a flip-flop is not stable prior to the arrival of the clock edge, potentially resulting in the incorrect latching of data.

Hold Violation: Data input instability, occurring immediately following the clock edge, may result in data corruption due to the flip-flop's inability to properly latch the input.

Steps to Fix Setup Violations

Analyze Timing Reports: Use timing analysis tools to identify the specific paths causing setup violations. Look for critical paths and their delays.

Optimize Logic:

- Restructure Logic: Simplify or reorganize the logic to reduce the combinational path delays.

- Use Faster Logic Elements: If possible, replace slower gates with faster alternatives.

Increase Clock Period: If feasible, consider increasing the clock period to allow more time for signals to propagate.

Reposition Components: During placement, try to reduce the distance between flip-flops and their driving logic to minimize routing delay.

Add Buffers: Inserting buffers in critical paths can help drive the load and reduce delay.

Adjust Constraints: Review and adjust constraints in your design tools, such as clock definitions and false paths, to ensure accurate timing analysis.

Use Multi-Cycle Paths: If certain paths do not need to meet the setup time in every clock cycle, you can define them as multi-cycle paths.

Steps to Fix Hold Violations

Analyze Timing Reports: Similar to setup violations, use timing analysis tools to identify paths with hold violations.

Add Delay: Insert delay elements (like buffers) to increase the signal delay on paths that are too fast.

Reposition Components: Move the flip-flops or their driving logic closer to each other to minimize the routing delay.

Reduce Load: If possible, redesign the logic to decrease the capacitance seen by the flip-flops.

Use Faster Cells: Replace slower cells with faster ones that can provide the required timing margins.

Clock Skew: If applicable, consider adjusting clock skew to provide additional hold time for critical paths.

What is blockage and halos in physical design in VLSI?

Blockages:

Let’s assume that for some reason you don’t want to place any logic (can be a specific set of cells as well) or you don't intend to allow certain metal layers in a specific area or you are reserving a space for later stage additions (could be a room for top design related ) :

in all these cases you can use ‘blockages’ to reserve/restrict/block a specific area either from preventing std cell placement or avoiding specific layer metal shapes.

  1. placement blockages

  2. routing blockages.

Halos:

In the design of a System-on-Chip (SoC) comprising multiple sub-IPs/blocks, the physical implementation of both the top-level SoC and its sub-blocks is typically managed by distinct teams. To ensure that the physical layout adheres to design rules and is fabrication-ready upon integration, a coordinated approach is essential. This involves guidance from the methodology, fabrication, and process teams to establish standardized layout patterns for all designs, particularly at their boundaries. This best practice enables the top-level designer to anticipate interface patterns and implement integration strategies effectively. To facilitate this, the implementation of HALO cells, incorporating recommended patterns for various edge types, is proposed. Both sub-blocks and the top-level design must utilize these HALO cells appropriately on all sides. 

Why do we start with clock routing first in physical design?

Typically, most designs incorporate clocks, with a substantial number of sequential cells governed by these clock signals. The prioritization of routing is not solely determined by whether clocks or data are considered first; rather, it hinges on factors such as criticality, vulnerability to variations, operational frequency, load magnitude, and the distance required for signal propagation to all sinks. In synchronous designs, clocks serve as the primary control signals for sequential cells. Given the clock network's high load, operational frequency, and stringent requirements for minimal variation, clock routing is initiated before data signal routing. This approach allows for greater flexibility in utilizing various Non-Design Rule (NDR) options and specific metal layers to meet specific timing objectives. Furthermore, in certain instances, the routing of exceptionally critical signals may commence even before clock routing.

Double Patterning

Double patterning is a lithographic technique employed in advanced integrated circuit manufacturing processes. It allows for the creation of sub-nanometer features on chips using existing optical lithography systems.

The implementation of double patterning presents certain challenges, including elevated mask and lithography expenses, and constraints on circuit layout, which can affect design complexity, device performance, variability, and density.

Double patterning mitigates diffraction effects in optical lithography, which arise because the minimum dimensions of advanced process nodes are significantly smaller than the 193nm wavelength of the light source. These diffraction effects compromise the accuracy of deep sub-micron patterns, causing blurring and potentially preventing the replication of small features from the mask onto the wafer.

To mitigate diffraction effects, such as shorts and opens, the original mask is partitioned into two distinct masks, designated as Mask A and Mask B. This approach, however, escalates mask costs (lithography expenses) due to the implementation of double patterning and introduces additional Design Rule Checking (DRC) constraints.

To address the increasingly significant diffraction challenges associated with each new process node, several reticle enhancement techniques have been developed.

Phase-shift masks, introduced at the 180nm process node, modify the phase of light passing through specific mask regions. This alteration influences diffraction patterns, thereby mitigating the defocusing effects associated with mask dimensions smaller than the illumination wavelength. A drawback of phase-shift techniques is the increased complexity and cost of mask fabrication.

Optical Proximity Correction (OPC) techniques involve pattern distortion on the mask to counteract diffraction effects. This is achieved, for example, by adding small "ears" to the corners of a square feature on the mask, ensuring sharp definition on the wafer. While effective, this technique introduces layout restrictions, computational overhead in design, and increases the time and cost associated with mask production..

TIE CELLS

To prevent direct gate connections to the power or ground network, tie-high and tie-low cells are employed. Within this design, certain cell inputs may necessitate a logic 0 or logic 1 value. Unused cell inputs are also connected to ground or power nets, as leaving them unconnected is not permissible. Rather than directly connecting these inputs to the VDD/VSS rails/rings, they are connected to specialized cells within the library, known as TIE cells

The tie-high, tie-low circuit, featuring tie-high and tie-low outputs, incorporates a regenerative device designed for connection to both outputs, along with at least one PMOS device and one NMOS device, intended for connection to a high voltage and a low voltage, respectively.

In integrated circuit (IC) applications, it is not always necessary to utilize all inputs. Unused inputs should be consistently maintained in a stable logic state, rather than left floating, as unpredictable or intermediate logic states can lead to unpredictable and inconsistent logical outcomes. This is a critical concern that IC designers actively address.

To ensure stability, small circuits are incorporated into ICs. These circuits typically provide at least two outputs: one consistently high and another consistently low. These outputs are then used to connect IC inputs to either a high or low state, thereby locking unused inputs into a stable logic state.

However, conventional circuit designs present several challenges. Many designs utilize at least four transistors, which consume valuable chip area and may necessitate additional, costly manufacturing steps. Furthermore, some designs, while using only three transistors, often exhibit limited tolerance to electrostatic discharge (ESD).

Consequently, there is a need in the field of integrated circuit design for improved, smaller circuits with enhanced ESD tolerance, capable of effectively tying unused IC inputs to either a high or low state.

Regarding the rationale for employing such circuits, gate oxide is inherently thin and sensitive to voltage surges. Certain manufacturing processes may restrict the direct connection of gates to power rails due to the potential for gate oxide damage from voltage surges, such as ESD events. Therefore, tie cells, which utilize diode-connected n-type or p-type devices, are often employed. This approach prevents direct gate connections to either power or ground.

This is the foundry's rationale for ESD protection against surges. Examining the schematic of the tie cells in a standard cell library may reveal an inverter configuration with its input connected to either VDD (for tie-low) or VSS (for tie-high). While this configuration still connects the tie cell's gate to the power rails, it offers benefits such as reduced leakage current. Additionally, it simplifies the process of rewiring during Engineering Change Orders (ECOs), particularly when swapping a 1'b1 for a 1'b0.

Skin Effect Impact on Semiconductor Wires

Currently, our analysis has assumed a linear and constant resistance for a semiconductor wire, which is generally accurate for most semiconductor circuits. However, at elevated frequencies, the skin effect introduces a frequency-dependent resistance.

High-frequency currents exhibit a tendency to concentrate on the conductor's surface, with current density decreasing exponentially with depth. The skin depth, denoted as d, is defined as the depth at which the current diminishes to e⁻¹ of its nominal value, and is expressed as:

Given the signal frequency (f) and the permeability of the surrounding dielectric (U), which typically approximates the permeability of free space (m = 4p ´ 10-7 H/m), the skin depth for Aluminum at 1 GHz is calculated to be 2.6 mm.

The impact of the skin effect can be approximated by assuming a uniform current distribution within an outer shell of the conductor, with a thickness denoted as d, as illustrated in the provided figure for a rectangular wire. Consequently, the effective cross-sectional area of the wire is approximated to 

we obtain the following expression for the resistance (per unit length) at high frequencies (f > fs):

The increased resistance at higher frequencies may cause an extra attenuation and hence distortion of the signal being transmitted over the wire. To determine the on-set of the skin-effect, we can find the frequency fs where the skin depth is equal to half the largest dimension (W or H) of the conductor. Below fs the whole wire is conducting current, and the resistance is equal to (constant) low-frequency resistance of the wire. From Eq. (4.6), we find the value of fs:

Physical design QNA

1. What is floorplanning?

    A. Floorplanning is the process of strategically positioning blocks and macros within the chip or core area, thereby defining routing regions. This process determines the die size and establishes wire tracks for standard cell placement. It also generates power straps and specifies Power Ground (PG) connections, as well as I/O pin/pad placement information. In essence, floorplanning involves determining macro placement, power grid generation, and I/O placement.

2. What constitutes a well-executed floorplan?

    A. A robust floorplan should adhere to the following constraints:

    * Minimize the overall chip area.

    * Facilitate the routing phase (ensuring routability).

    * Enhance performance by reducing signal delays.

3. What inputs are required for floorplanning?

    A. The following inputs are essential for floorplanning:

    * Synthesized Netlist (.v, .vhdl)

    * Design Constraints (SDC – Synopsys Design Constraints)

    * Physical Partitioning Information of the design

    * IO Placement file (optional)

    * Macro Placement File (optional)

    * Floorplanning Control parameters

4. What are the outputs of the floorplanning process?

    A. The floorplanning process yields the following outputs:

    * Die/Block Area

    * I/Os Placement

    * Macros Placement

    * Power Grid Design

    * Power Pre-routing

    * Standard cell placement areas

5. Given a netlist comprising 500k gates, how can the die area and floorplanning be estimated?

    A. There are two primary methods for estimating die area:

    Method 1:

    Each cell possesses an area value specific to the chosen library. By examining each cell and multiplying its count by its corresponding area from the vendor's library, a density factor can be applied. Typically, a standard design achieves approximately 80% density after placement. This data allows for an estimation of the required die area.

    Method 2:

    Alternatively, the design can be loaded into an implementation tool. By adjusting the floorplan (x and y coordinates), the initial utilization can be set to approximately 50% to 60%.

The approach is contingent upon the quality and completion status of the netlist, specifically the degree of completion, such as 75%, 80%, or 90%.

6. What is the methodology for floor planning in multi-Vdd designs?

A. The initial step involves defining the power domains, followed by the implementation of power rings for each domain and the addition of power stripes to supply power to standard cells.

7. What is the definition of core utilization percentage?

A. The core utilization percentage represents the proportion of the core area utilized for cell placement. This is calculated as the ratio of the total cell area (including hard macros, standard cells, and soft macro cells) to the core area. For instance, a core utilization of 0.8 indicates that 80% of the core area is used for cell placement, with 20% available for routing.

8. Does an increase in core utilization to 90% potentially lead to macros being placed outside the core area, and does this imply a reduction in width and height?

A. Operating at 90% utilization may introduce congestion and routing challenges, potentially hindering routing within the designated area. While it may be feasible to accommodate this utilization level initially, subsequent timing optimizations, such as upsizing and buffer insertion, can increase the size requirements. In such cases, adjustments to the floorplan may be necessary. Therefore, a safer approach is to maintain a utilization range of 70% to 80%.

9. Why is it necessary to remove all placed standard cells and then write out the floorplan in DEF format? What is the purpose of the DEF file?

A. The DEF file primarily focuses on the floorplan size. This method is employed to obtain an abstract representation of the floorplan. By saving and loading this file, the abstract can be restored, eliminating the need to redo the floorplan.

10. Can area recovery be achieved by downsizing cells along paths with positive slack?

A. Yes, area recovery can be accomplished by downsizing cells on paths exhibiting positive slack. Additionally, the removal of unnecessary buffers can also contribute to area recovery.

11. How can IR drop be managed by adjusting the number of power straps? While increasing the number of power straps reduces IR drop, what is the optimal number of straps to implement? How is the required number of straps calculated? What potential issues may arise from an excessive number of straps?

A. Tools such as Voltagestrom and Redhawk can be utilized to calculate IR drop if it is excessive. Based on the results, additional straps can be added. Through repeated project experience, the appropriate number of straps can be determined without the need for these tools. While calculations exist, they are approximate. An excessive number of straps can lead to routing congestion and impact the area. For further details on determining the number of power straps required for a design, please refer to the provided link.

12. aprPGConnect is used for the logical connection of all VDD and VSS nets of all modules. How are all VDD and VSS nets connected to the global VDD/VSS nets before placement?

A.

The aprPGConnect facilitates the logical connection of all VDD and VSS nets across all modules. This is for physical connection.

CCS vs. NLDM: A Comparison of Delay Models

Introduction to Delay Models

• CCS stands for Composit Current Sourse Model, and NLDM stands for Non-Linear Delay Model.

• Both CCS & NLDM are delay models used in timing analyze.

Key Differences in Driver Modeling

• NLDM uses a voltage source for driver modeling

• CCS uses a current source for driver modeling

Advantages of CCS over NLDM

• The issues with NLDM modeling is that, when the drive resistance RD becomes much less than Znet(network load impedance), then ideal condition arises i.e Vout=Vin.

• Which is impossible in practical conditions.

• So with NLDM modeling parameters like the cell delay calculation, skew calculation will be inaccurate.

• That is the reason why we prefer CCS to NLDM