Clock Uncertainty : The Time difference between the arrival of the clock signal at the register in one clock domain or between any two clock domains
Uncertainty is caused by following factors:
skew can be classified into different skews:
It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically caused by clock generator circuitry, noise, power supply variations, interference from nearby circuitry etc. Jitter is a contributing factor to the design margin specified for timing closure.
Based on how it is measured in a system, jitter is of following types:
Period jitter
Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles(say 10K cycles). It can be specified an average value of of clock period deviation over the selected cycles(RMS value) or can be the difference between maximum deviation & minimum deviation within the selected group(peak-to-peak period jitter).
Cycle to cycle jitter :
In frequency domain, the effect being measured is phase noise. It is the frequency domain representation of rapid, short-term, random fluctuations in the phase of a waveform. This can be translated to jitter values for use in digital design.
Please note all the above jitters are effectively the same phenomenon, but different way of measuring and representing the effect for use in design flow. The jitter number thus obtained is used to specify the design margin using the command “set_clock_uncertainty”.
Effects
Since the jitter affects the clock delay of the circuit and the time the clock is available at sync points, setup and hold of the path elements are affected by it. Depending on whether the jitter causes the clock to be slower or faster, there can be setup hold or setup violations in an otherwise timing clean system. This will in turn lead to performance or functional issues for the chip. So it is necessary that the designer knows the jitter values of the clock signal and need to be considered while analyzing timing.
Uncertainty is caused by following factors:
- clock skew
- clock jitter
- cross talk
- Skew is the difference in clock arrival time across the chip.
- Clock Skew is the temporal difference between the arrival of the same edge of a clock signal at the Clock pin of the capture and launch flops.
- Signal takes time to move from one location to another. Clock latency is the time taken by a clock signal to move from the clock source to the clock pin of a particular flip-flop. Clock skew can alternatively be defined as the difference between capture and launch flop delay.
The clock should ideally reach the clock pin of all the flip-flops in a design at the same time, resulting in a zero skew. However, this is not attainable owing to varying wire-interconnect lengths and temperature changes.
What is the reason for skew in a design?
A skew in a design occurs when a flip-flop is put near the clock source and another flip-flop is placed at the far end of the core region. In practice, the skew cannot be zero due to the disparity in connecting lengths. To address this, a user-specified number is provided to obtain correct pre-CTS timing data. After the clock tree is constructed, the real skew values are accessible, and the uncertainty is limited to the Jitter value alone.
The time difference/delta between the launch flip flop and capture flip flop or
it refers to the absolute time diff between the clock signal arrival between the two points in the clock network
it refers to the absolute time diff between the clock signal arrival between the two points in the clock network
Tskew =Tlaunch_clk - Tcapture_clk
skew can be classified into different skews:
- +ve skew: Positive clock skew, In this case, the capture clock delay is greater than the launch clock latency. Positive skew is advantageous for setup timing. Due to the inclusion of skew, the capture clock is delayed by a few ns. Therefore the timing path requires one clock period and Skew margin to match the setup requirement.
- -ve skew: Negative Skew is beneficial for hold time since it delays the fresh launch. Because of the delay in launching the new data, the prior data will be effectively recorded and will not be overwritten. However, negative skew is detrimental to setup timing.
- Local skew: The disparity in latency between two related flops in a design is referred to as local skew.
- Global skew: is the difference in clock delay between two unrelated flops or the difference between the longest and shortest clock paths in the design.
- Usefull Skew :Useful skew is the skew that is purposefully introduced into the design to satisfy timing. It is particularly introduced in clock pathways where timing is failing, so that timing is passed in that path. However, useful skew cannot be applied arbitrarily. This must be done with caution, ensuring that the margin is accessible in both the preceding and subsequent time paths. The uncontrolled insertion of skew might result in further timing violations rather than resolving them. It may be used to correct both setups and hold errors
It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically caused by clock generator circuitry, noise, power supply variations, interference from nearby circuitry etc. Jitter is a contributing factor to the design margin specified for timing closure.
Based on how it is measured in a system, jitter is of following types:
Period jitter
Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles(say 10K cycles). It can be specified an average value of of clock period deviation over the selected cycles(RMS value) or can be the difference between maximum deviation & minimum deviation within the selected group(peak-to-peak period jitter).
Cycle to cycle jitter :
C2C is the deviation in cycle of of two adjacent clock cycles over a random number of clock cycles. (say 10K). This is typically reported as a peak value within the random group.This is used to determine the high frequency jitter.
Phase jitter:
In frequency domain, the effect being measured is phase noise. It is the frequency domain representation of rapid, short-term, random fluctuations in the phase of a waveform. This can be translated to jitter values for use in digital design.
Please note all the above jitters are effectively the same phenomenon, but different way of measuring and representing the effect for use in design flow. The jitter number thus obtained is used to specify the design margin using the command “set_clock_uncertainty”.
Effects
Since the jitter affects the clock delay of the circuit and the time the clock is available at sync points, setup and hold of the path elements are affected by it. Depending on whether the jitter causes the clock to be slower or faster, there can be setup hold or setup violations in an otherwise timing clean system. This will in turn lead to performance or functional issues for the chip. So it is necessary that the designer knows the jitter values of the clock signal and need to be considered while analyzing timing.
Cross Talk
Swtiching of the signal in one net will effect the signal in neighboring net due to cross coupling capacitance, know as Cross Talk. This noise will affect the functionality of chip
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