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PD MCQ

on April 22, 2023

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scan chain REORDERING , why it is required

Scan chain reordering is an optimization technique to ensure scan chains are connected in more efficient way – based upon the placement of the flip-flops. At initial stage , we donot have the placement information, so we just stitch the flops register by register. The tools will stitch the flops randomly to form a scan chain before placement. For proper understanding flops are numbered and two scan chains are stitched in the screen shot shown below. But after placement it might be possible that the two flops stitched at initial stage of a different block sits far from each other when the placement is done. So if we keep the same scan chain order, we will face the placement congestion and timing congestion and more routing resources are required. We can see from above screenshot, depending on the timing and placement congestion flops are placed at different locations when compared to before placement figure. This results in usage of more resources, space congestion increases and also t

Recovery Time, Removal Time

Recovery Time: Recovery time is the minmium time that as asynchronous control signal must be stable before the clock active- edge transition. In other words, this check ensures that after the asynchronous signal become inactive, there is adequate time to recover so that the next active clock edge can be effective. Consider the time as show in below figure, between an asynchronous reset becoming inactive and the clock active edge of a flip-flop. If the active clock edge occurs too soon after the release of reset, in this case the state of the flip-flop may be unknow. Therefore it is required to have minimum time for asynshronus control signal to become stable. Recovery time is similar to setup time . Removal Time: Removal time is the minimum length of time that an asynchronous control must be stable after the clock active edge transition. This check ensures that the active clock edge has no effect because the asynchronus control signal remains active until removal time after the acti

Fault Class Hierarchies in DFT

Faults list in design are categorized into sub categories. Faults class are mainly divided into Testable (TE)–> Faults can be tested by some patterns. Untestable (UT)–> Faults foe which no pattern exits to detect the faults Testable Faults : There are four sub category under TE. DETECTED(DT) POSDET(PD) ATPG UNTESTABLE(AU) UNDETETED(UD) Detected ( DT) : The Faults which are detected during the ATPG process are categories under DT det_simulation(DS): The faults detected when the tools performs simulation det_implication(DI): The faults detected when the tool performs learning analysis POSDET(PD) : The Possible detected, faults includes all the faults that fault simulation identifies as possible detected posdet_testable(PT): Potentially detectable posdet faults.With higher abort limit we can reduce the number of these faults posdet_untestable(PU): These are proven ATPG untestable and hard undetectable faults. ATPG_UNTESTABLE(AU) : This fault class includes all the faults for which

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