DFT:Ad-hoc methods, Structured methods,Scan cell

Design for Testability (DFT) is required to guarantee the product quality, reliability, performances, etc. Design for Testability refers to those design techniques that

  • Enhances testability of device
  • Ease ability to generate vectors
  • Reduce test time
  • Reduce the cost involved during test

There are different methods to implement the DFT Logic for Digital circuits which are listed below

  • Ad-hoc methods: Good design practices learnt through experience and those methods are used as guidelines
    • Avoid combinational feedback
    • All flip flops must be initializable
    • Avoid redundant and large fanin gates
    • Provide test control for the signals which are not controllable
    • While designing test logic we have to consider the ATE requirements

Ad-hoc methods had few disadvantages, and these gives more advantage to Structured methods.

  • Disdvantages od ad-hoc DFT methods:
    • Experts and tools not always available
    • Test generation is often manual with no guarantee of high fault coverage
    • Design iterations may be necessary
  • Structured Methods: Structured DFT provides a more systematic and automatic approach to enhancing design testability. Structured DFT’s goal is to increase the controllability and observability of a circuit. Various methods exist for accomplishing this. The most common is the scan design technique, which modifies the internal sequential circuitry of the design.
    • Scan: In the design all the flip flops are converted to scan flip flop.
    • Boundary Scan
    • Built-in self-test

we have came across the scan flip flop, and you may be wondering, what would be the difference between a norml flip flop and a scan flip flop. Below pictorial representation give clear picture about a flop and scan flop.

D Flip Flop
Scan D Flip Flop

TM represents Test Mode signal and this signal should be 1 during DFT testing and 0 for functional model.