Fan-Out of the gate is defined as number of gate inputs it can drive. Every cell/gate will have limitations and we can get the maximum fan limits from LIB file which are provided by vendor or foundry. If Fan out violation occurs for a design or on pin, we can remove the violation by inserting a buffer.
For example, consider a two input OR gate which has a max fan out limit of 3. Assume in a design this OR gate is connected to 5 loads thus violating the Fan out violation. Violation can be removed by inserting a buffer with fan-out more than 3 as shown below. After inserting the buffer, the OR gate will have a fan-out of 3 which is within the limits.
Fig 1 : Fan out of OR gate with out buffer
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