Posts

scan chain REORDERING , why it is required

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Untestable faults in DFT

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Fault Class Hierarchies in DFT

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Implement the inverter using nand/NOR gate

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Different ways of Digital design representation

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Simplistic view of ASIC DESIGN flow

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chisel:Registers

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does knowlege on Location of MEMORIES was important during mbist implementation

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CHISEL:multiplexer

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Techniques to reduce the patterns count without losing coverage

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What are the deciding factors for a scan desgin

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DFT:Ad-hoc methods, Structured methods,Scan cell

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CHISEL:Combinational circuits

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