Posts

does knowlege on Location of MEMORIES was important during mbist implementation

CHISEL:multiplexer

Techniques to reduce the patterns count without losing coverage

What are the deciding factors for a scan desgin

CHISEL:Combinational circuits

Vi Editor Series III

CHISEL:DATA TYPES

Types of DFT Logic

T3 Violation in DFT

CHISEL

Utilisation Factor

Full Adder

How to remove maximum fan out violation for a cell?

Target Libraries, Link Libraries, Physical Libraries

Perl Series III

Half adder

Why NAND gate is preffered over NOR gate

Test coverage, Fault coverage

Universal Gates

Multi Voltage Domain